SystemVerilog Scheduling Regions

Step through one posedge clk timestep and see which region each statement runs in.

Step 1 / 9
Preponed
Timestep begins
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Preponed: sample for assertions
Active: blocking, assign, =
Inactive: #0 delays
NBA: LHS of <= writes
Observed: assertion eval
Reactive: program blocks
Postponed: $monitor, $strobe